Expand description
Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the LCR_H Register.
- If the FIFO is disabled, this bit is set when the receive holding register is empty.
- If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
Enums§
- Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the LCR_H Register.